A stacked memory has been developed as a nonvolatile semiconductor storage device. Division of a charge accumulation layer and a control electrode formed on side surfaces of one semiconductor pillar into plural pieces in a cross-section perpendicular to a stacking direction of a stack of insulating films and control electrode films is studied to improve an integration degree of the stacked memory. These charge accumulation layers and control electrodes are formed by cross-point processing. In the cross-point processing, after a plurality of trenches are formed in a stack, a plurality of shallow trench isolation films that perpendicularly intersect with an extending direction of the trenches are formed. Memory holes are formed at cross-points between gaps between adjacent ones of the shallow trench isolation films and the trenches, respectively. The charge accumulation layers and the control electrodes are formed on both sides of exposed portions of the stack in the memory holes.
However, the shallow trench isolation films used in the cross-point processing are, for example, insulating films such as a silicon dioxide film and etching thereof produces many depositions. Therefore, a process conversion difference is large and the memory holes become wide at top ends and narrow at bottom ends when the shallow trench isolation films are processed. In this case, a gate area (a gate width×a gate length) of a memory cell and the threshold voltage thereof vary according to the position of the memory cell in the stacking direction. This leads to variation in a write voltage or an erase voltage. Furthermore, a cross-sectional area of the semiconductor pillars formed in the memory holes also becomes large at top portions and small at bottom portions. Therefore, cell currents in memory cells at the bottom portions of the semiconductor pillars are adversely reduced.